The present invention relates to CSP (chip size package) semiconductor devices. Techniques have been known in which in a semiconductor device, a plurality of electrode pads, each having a tenon-like conformation in plan view, are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. Each of the electrode pads has a narrow, probing portion for testing or analyzing, and a wide, bonding portion which is wire-bonded to a package terminal. By this structure, the pad pitch is reduced, while the influence of probe marks is lessened (see Japanese Laid-Open Publication No. 2000-164620.)
CSP semiconductor devices were developed to reduce package size. Examples of the CSP semiconductor devices include a semiconductor device formed by flip-chip (face-down) bonding a semiconductor chip to a carrier which is used for external connection with the semiconductor chip. If concentrated stress applied to the bottom-face corners of the semiconductor chip during testing is taken into account, formation of circuit elements is restricted so that no circuit elements are formed in predetermined regions near the corners on the semiconductor chip surface (see Japanese Laid-Open Publication No. 2002-252246.)
A POE (pad on element) technique may be employed for CSP semiconductor devices. By a POE technique, electrode pads are formed on input/output cells that include circuit elements formed so as to be peripherally arranged on the semiconductor chip surface. This structure allows the semiconductor chip to be decreased in size.
Nevertheless, if a zigzag electrode-pad arrangement is also adopted, a reduced pad pitch creates difficulties in designing a CSP carrier that can accommodate regions near the corners on the semiconductor chip surface. More specifically, of the interconnect patterns formed on the carrier surface, those patterns that are bump-bonded to the inner pad arrays of the semiconductor chip, and vias in the carrier become complex, such that so-called “via generation” cannot be performed from the inner pad arrays near the corners. This causes an increase in the size of the semiconductor chip.